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Bangladesh Chemical Industries Corporation

Post: Assistant Programmer
Exam Taker: BUET, Exam Date: 14.02.2025
1. How to implement stack using two queues?

Implement Stack Using Two Queues

A Stack follows LIFO (Last In First Out), while a Queue follows FIFO (First In First Out). We can implement a Stack using two Queues (Q1 and Q2) by making the Stack operations behave like LIFO.

Method (Costly Push / Easy Pop)

Idea: Always keep the newest element at the front of Q1, so that Pop works like Stack.

Operations:

1) Push(x):

  • Enqueue x into Q2.
  • Move all elements from Q1 to Q2 (dequeue from Q1 and enqueue to Q2).
  • Swap Q1 and Q2 (now Q1 has the new order).

2) Pop():

  • If Q1 is empty → Stack is empty.
  • Dequeue from Q1 and return it (this is the top element).

3) Top/Peek():

  • Return the front element of Q1.

4) isEmpty():

  • If Q1 is empty → true, else false.

Time Complexity:

Push = O(n), Pop = O(1), Top = O(1)

Two Queue ব্যবহার করে Stack Implement

Stack হলো LIFO (Last In First Out) ভিত্তিক, আর Queue হলো FIFO (First In First Out) ভিত্তিক। দুইটি Queue (Q1, Q2) ব্যবহার করে Stack Implement করা যায়, যেখানে Operation গুলোকে LIFO-এর মতো আচরণ করানো হয়।

Method (Costly Push / Easy Pop)

Idea: সবসময় নতুন Element-কে Q1-এর Front-এ রাখা, যাতে Pop করলে Stack-এর Top পাওয়া যায়।

Operations:

1) Push(x):

  • x কে Q2-এ Enqueue করো।
  • Q1-এর সব Element Dequeue করে Q2-এ Enqueue করো।
  • তারপর Q1 এবং Q2 Swap করো (এখন Q1-এ নতুন Order থাকবে)।

2) Pop():

  • যদি Q1 Empty হয় → Stack Empty।
  • Q1 থেকে Dequeue করে Return করো (এটাই Top Element)।

3) Top/Peek():

  • Q1-এর Front Element Return করো।

4) isEmpty():

  • Q1 Empty হলে true, না হলে false।

Time Complexity:

Push = O(n), Pop = O(1), Top = O(1)

2. Convert 10.12.2.0 to 10.12.3.255 CIDR notation

Convert 10.12.2.0 – 10.12.3.255 to CIDR Notation

Step 1: Identify the Range

Starting IP: 10.12.2.0

Ending IP: 10.12.3.255

Step 2: Check the Third Octet

The range covers 10.12.2.0 to 10.12.3.255 → which means 2 continuous blocks (2 and 3).

Step 3: Count Total IP Addresses

Each Class C block (/24) contains 256 IPs.

Here we have 2 blocks → 256 × 2 = 512 IP addresses.

Step 4: Find CIDR Prefix

512 = 2⁹

Total bits in IPv4 = 32

32 − 9 = 23

Final Answer:

The CIDR notation is 10.12.2.0/23

Subnet Mask = 255.255.254.0

10.12.2.0 – 10.12.3.255 কে CIDR Notation-এ রূপান্তর

ধাপ ১: Range নির্ধারণ

Starting IP: 10.12.2.0

Ending IP: 10.12.3.255

ধাপ ২: Third Octet

এই Range 10.12.2.0 থেকে 10.12.3.255 পর্যন্ত → অর্থাৎ পরপর ২টি Block (2 ও 3)।

ধাপ ৩: মোট IP সংখ্যা নির্ণয়

প্রতিটি /24 Block-এ 256 টি IP থাকে।

এখানে ২টি Block → 256 × 2 = 512 টি IP।

ধাপ ৪: CIDR Prefix নির্ণয়

512 = 2⁹

IPv4-এ মোট Bit = 32

32 − 9 = 23

Final Answer:

CIDR Notation = 10.12.2.0/23

Subnet Mask = 255.255.254.0

3. What is Multiplexer? Differentiate between D Flip-Flop, D Latch.

1. Multiplexer (MUX)

Multiplexer (MUX) is a combinational logic circuit that selects one input from multiple input lines and forwards it to a single output line.

It has n selection lines to choose one of 2ⁿ input lines. It is used to reduce the number of data lines and efficiently transmit data.

Example: A 4-to-1 MUX has 4 input lines, 2 select lines, and 1 output line.

2. Difference between D Flip-Flop and D Latch

D LatchD Flip-Flop
Level triggered device.Edge triggered device.
Output changes when Enable signal is active.Output changes only at clock edge (rising or falling).
Simple design and faster.More complex design.
Less reliable in synchronous circuits.More reliable in synchronous circuits.

১. Multiplexer (MUX)

Multiplexer (MUX) হলো একটি Combinational Logic Circuit, যা একাধিক Input Line থেকে একটি নির্দিষ্ট Input নির্বাচন করে একটিমাত্র Output-এ প্রেরণ করে।

এতে n টি Select Line থাকে, যার মাধ্যমে 2ⁿ টি Input থেকে একটি নির্বাচন করা যায়। এটি Data Line কমাতে ব্যবহৃত হয়।

উদাহরণ: 4-to-1 MUX-এ ৪টি Input, ২টি Select Line এবং ১টি Output থাকে।

২. D Flip-Flop ও D Latch-এর পার্থক্য

D LatchD Flip-Flop
Level Triggered Device।Edge Triggered Device।
Enable Signal সক্রিয় থাকলে Output পরিবর্তন হয়।Clock-এর Edge-এ Output পরিবর্তন হয়।
Design সহজ ও দ্রুত।Design তুলনামূলক জটিল।
Synchronous Circuit-এ কম নির্ভরযোগ্য।Synchronous Circuit-এ বেশি নির্ভরযোগ্য।
4. Consider the set of 5 processes whose arrival time and burst time are given below
Process IdArrival timeBurst time
P105
P213
P321
P432
P543
If the CPU scheduling policy is Round Robin with time quantum = 2 unit, calculate the average waiting time and average turn around time.

5. Difference between class and structure

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