Microcredit Regulatory Authority
Post: Assistant Maintenance Engineer
Exam Date: 2022
Frame Size: 1500B
Headers:
- IP Header: 20B
- UDP Header: 8B
- Total Header Size: 28B
Total UDP Payload Data: 1500B – 28B = 1472B
Total Bits Sent Per Second:
- Payload per packet = 1472B × 8 bits = 11776 bits
- Total bits sent per second = 11776 × 50 = 588800 bps
Throughput: 588800 bps or 588 kbps
Using Shannon’s equation:
\[ C = B \log_2(1 + SNR) \]
\[ B = 300 \, \text{Hz}, \, SNR \, \text{(in dB)} = 3 \]
\[ SNR = 10^{0.3} \]
\[ C = 300 \log_2(1 + 10^{0.3}) \]
\[ C = 300 \log_2(2.995) \]
\[ C = 300 \times 1.585 \]
\[ C = 474 \, \text{bps} \]
Answer:
Channel Capacity = 474 bps
- A hash value of the original message or file is generated.
- The hash value is encrypted using the sender’s private key to create the digital signature.
- The original message or file is sent along with the digital signature.
- The receiver decrypts the digital signature using the sender’s public key.
- The decrypted hash is compared with a newly generated hash of the received message.
- If both hashes match, the message is authentic.
- If they do not match, the message has been tampered with.
- প্রথমে message বা file-এর একটি hash value তৈরি করা হয়।
- এই hash value sender-এর private key দিয়ে encrypt করে digital signature তৈরি করা হয়।
- Original message বা file-এর সাথে digital signature পাঠানো হয়।
- Receiver sender-এর public key ব্যবহার করে signature decrypt করে।
- Decrypt করা hash এবং প্রাপ্ত message-এর নতুন hash তুলনা করা হয়।
- যদি দুইটি hash এক হয়, তবে message authentic।
- Hash mismatch হলে message পরিবর্তন হয়েছে বলে বোঝা যায়।
An 8:1 Multiplexer (MUX) is a combinational logic circuit with:
- 8 input lines: I0, I1, I2, I3, I4, I5, I6, and I7.
- 3 select lines: S0, S1, and S2.
- 1 output line: Y.
The logic levels on the select lines S0, S1, and S2 determine which input line will be transmitted to the output line Y.
To derive the logic expression for the output (Y) and understand its working, the function table (truth table) is required. This table provides the relationship between the select lines and the input-output operation of the multiplexer.
Block Diagram:
The function table for an 8:1 multiplexer with inputs (I0 to I7) and select lines (S0, S1, S2) is shown below.
| S2 | S1 | S0 | Output (Y) |
|---|---|---|---|
| 0 | 0 | 0 | I0 |
| 0 | 0 | 1 | I1 |
| 0 | 1 | 0 | I2 |
| 0 | 1 | 1 | I3 |
| 1 | 0 | 0 | I4 |
| 1 | 0 | 1 | I5 |
| 1 | 1 | 0 | I6 |
| 1 | 1 | 1 | I7 |
Y = S2 . S1 . S0 . I0 +
S2 . S1 . S0 I1 +
S2 . S1 S0 . I2 +
S2 . S1 S0 I3 +
S2 S1 . S0 . I4 +
S2 S1 . S0 I5 +
S2 S1 S0 . I6 +
S2 S1 S0 I7
From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented using 8 AND gates, 1 OR gate, and 7 NOT gates. When the enable pin is set to 1, the multiplexer will be disabled. If the enable pin is 0, the select lines will determine the corresponding data input that passes through to the output.
